This invention relates to an output interface circuit for converting a signal level of CMOS (complementary metal oxide semiconductor) into a signal level of ECL (emitter coupled logic).
FIG. 1 exemplifies a conventional output interface circuit wherein a CMOS inverter comprised of a P-type MOS transistor 21 and an N-type MOS transistor 31 which are connected in series between first and second power supplies V.sub.DD1 and V.sub.SS1 has the output, 121, connected to the base of a bipolar transistor 51 which has its emitter connected to an output terminal 2 and its collector connected to a third power supply V.sub.DD2 to operate as an emitter follower, so that a signal of CMOS level applied to an input terminal 1 is converted into a signal of ECL comparable level. In the following description, bipolar transistors are all assumed to be of the NPN type. Typically, the output terminal 2 is connected to a termination power supply V.sub.TT through a transmission line 80 having a constant characteristic impedance and a terminating resistor 90. For example, the characteristic impedance of the transmission line and the resistance of the terminating resistor are selected to be 50 .OMEGA.. The conventional output interface circuit constructed as above is disclosed in, for example, ISSCC '82 Digest of Technical Papers, pp 248-249.
In the circuit of FIG. 1, the delay time of circuit is disadvantageously increased upon the rise of output signal as will be described with reference to FIG. 2. Operation waveforms appearing at various points in the FIG. 1 circuit are diagrammatically shown in FIG. 2. In FIG. 2, voltage waveforms appearing at input terminal 1, terminal 121 and output terminal 2 upon the rise of input signal (upon the fall of output signal) are designated by 2001, 2011 and 2021, respectively. Also, voltage waveforms appearing at input terminal 1, terminal 121 and output terminal 2 upon the input fall (upon the output rise) are designated by 2002, 2012 and 2022, respectively. As an example, the first power supply V.sub.DD1 is 0 (zero) volt (reference potential), the second power supply V.sub.SS1 is -5.2 volts, the third power supply V.sub.DD2 is 0 volt and the termination power supply V.sub.TT is -2.0 volts. When the low level (-5.2 volts) of CMOS level is applied to the input terminal 1, the N-type MOS transistor 31 is turned off and the P-type MOS transistor 21 is turned on to provide the high potential (about 0 volt) at the terminal 121, with the result that the base current flows through the bipolar transistor 51 to turn it on and a driving current is supplied from the power supply V.sub.DD2 to the output terminal 2. At that time, potential V.sub.o at the output terminal 2 is given by EQU V.sub.o =V.sub.DD1 -(.DELTA.+V.sub.BE).perspectiveto.-0.9 (volts) (1)
which corresponds to the high level of ECL level, where V.sub.BE .perspectiveto.0.7 volts represents the base/emitter voltage of bipolar transistor 51 and .DELTA., which can be designed to approximate 0.2 volts, represents a voltage drop across the P-type MOS transistor 21 under the conduction of the base current through the bipolar transistor 51. Subsequently, when the CMOS level at input terminal 1 changes to the high level (0 volt) as shown at 2001, the N-type MOS transistor 31 is turned on and the P-type MOS transistor 21 is turned off, thereby changing the high level at terminal 121 to the low level (-5.2 volts) as shown at 2011. At that time, the bipolar transistor 51 becomes non-conductive with its base current almost cut off when the potential at the terminal 121 falls below a level (about -1.5 V to about -1.2 V) which is higher than V.sub.TT (-2.0 V) by V.sub.BE (V.sub.BE being about 0.5 to 0.8 volts depending on the base current and temperature). The potential at output terminal 2 thus changes from a high level to the low level (-2.0 volts) as shown at 2021.
Subsequently, the potential at input terminal 1 changes from high level to low level as shown at 2002 and then, the potential at terminal 121 changes to the high potential as shown at 2012. During this operation, the supply of base current to the bipolar transistor 51 is insufficient before the potential at terminal 121 starting from -5.2 volts reaches the threshold level (-1.5 to -1.2 volts) and as a result the potential at output terminal 2 remains at the low level to considerably delay the output rise in comparison with the output fall as will be seen from FIG. 2.